The present invention relates to electronic integrated circuits of the type comprising configurable logic circuit arrays.
This invention finds particular utility in a configurable logic circuit array of the type as disclosed in our specification No. GB B-2180382 (the disclosure of which is incorporated herein by reference) in which the logic circuit array comprises a matrix of discrete sites or cells at each of which is a logic circuit which is adapted to perform a simple logic function. Typically the simple logic function is implemented by means of a two-input NAND gate.
An array of this type is capable of being programmed in such a manner as to configure the various NAND gates, as required, to perform various and different logic functions. One such function is known as a latching function and in the logic array as disclosed in specification No. GB B-2180382, a latching function may be implemented using four NAND gates.
This has the disadvantage that the greater number of latching functions that may be required from any logic array the fewer NAND gates remain for other required functions. This has the effect of reducing the overall effectiveness of the array.
An object of this invention is to overcome this disadvantage by providing an additional logic circuit for inclusion in each of the logic circuits at each discrete site to enable each site to have a greater programmable facility and thereby increase the overall utilization of the array.